Digital cycle system coordinator for traffic control system

ABSTRACT

A pair of periodic pulsating signals are generated at a master control station, such signals differing in frequency by a predetermined small amount. These two frequencies are chosen so that they will periodically arrive in phase with each other at intervals equal to a desired timing cycle. The signals from the master station are transmitted to coordinated intersections in a system where the signals are received by coordinators and digitally processed to generate a plurality of clock pulses, each of said clock pulses representing a finite increment of the total timing cycle. These timing pulses as referred to the commencement of the timing cycle are utilized to synchronize the local controller with the master station and to provide various desired timing offsets.

States atent Morgan et al. [4 Apr. 4, 1972 [541 DIGITAL CYCLE SYSTEM3,551,825 12/1970 Du Vivier et al. .340/41 COORDINATOR FOR TRAFFIC2,989,728 6/ 1961 Barker ..340/40 CONTROL SYSTEM PrimaryExammerl(athleen H. Claffy [72] Inventors: Daniel H. Morgan, Orange;Jackie E. Assistant ExaminerRandall P. Myers Herndon, Garden Grove, bothof Calif. Attorney-Sokolski & Wohlgemuth [73] Ass1gnce: 1:21:11;Sliecltirtaomcs Industries, Inc., Los [57] ABSTRACT [22] Filed, May 201969 A pair of periodic pulsating signals are generated at a mastercontrol station, such signals differing in frequency by a [21] Appl.No.: 826,167 predetermined small amount. These two frequencies arechosen so that they will periodically arrive in phase with each other atintervals equal to a desired timing cycle. The signals from the masterstation are transmitted to coordinated inter- [58] Fie'ld 41 g 42sections in a system where the signals are received by coordinators anddigitally processed to generate a plurality of 5 6] Reterences Citedclock pulses, each of said clock pulses representing a finite incrementof the total timing cycle. These timing pulses as UNITED STATES PATENTSreferred to the commencement of the timing cycle are utilized tosynchronize the local controller with the master station and garlz/er toprovide various desired timing u 1v1er 3,544,91 1 12/1970 Du Vivier etal1 340/41 13 Claims, 4 Drawing Figures PATENTEDAPR 4 I972 3, 654, 598

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1. a: J A 690 mi A h F l I I I I I I l I I l I l L SOKQSKI 8| VKHLGEMUTH ATTORNEYS DIGITAL CYCLE SYSTEM COORDINATOR FOR TRAFFIC CONTROL SYSTEMThis invention relates to traffic controllers and more particularly to adigital system for coordinating the operation of local trafficcontrollers from a master control station.

Traffic controllers located at succeeding intersections along a streetare generally synchronized from a master control station by means of acoordinating signal which is transmitted from the master station to eachof the remote controllers to establish a timing reference. This timingreference signal is utilized to coordinate the timing of the varioustraffic controllers in a desired manner with offsets in the timing ateach intersection being established to handle various trafficconditions.

In the prior art, such as described, for example, in US. Pat. No.2,989,728 issued June 20, 1961, the timing signals are transmitted fromthe master station as a pair of sine waves which differ slightly infrequency thereby establishing a timing cycle in accordance with thetime period between successive in phase conditions of the two sinewaves.

In these prior art systems, offset operation at the local controllers isestablished by means of potentiometers which are utilized to introducephase shift into one of the signals thereby changing the in phasecondition time of occurrence of such signals. This type ofimplementation has the shortcomings inherent in potentiometers of thistype such as the wear involved in the potentiometer wiper contacts whichdetracts from reliability of operation. Further, such potentiometers arebulky as compared with the semi-conductor type circuitry which isutilized in its stead in the instant invention. Also, it is difficult toaccurately set up the offset timing on potentiometers in the phase shifttype implementation of the prior art. It is even more difficult tomaintain this desired phase shift once it is set, due to the effects ofexternal influences which tend to cause erroneous phase shifts to occur.

The system of this invention overcomes the aforementioned shortcomingsof the prior art by providing a fully digital implementation in whichrather than using phase shift potentiometers for dividing up the timingcycle, this end result is rather achieved by dividing this cycle intoequal digital timing increments, each such increment being representedby a clock pulse. It is possible with the digital implementation of thisinvention to obtain a very fine division of the timing cycle, the clockpulses representing these divisions being highly accurate and reliableover long periods of operation. Further, timing offsets can be set intothe local controllers to a very high degree of accuracy merely bysetting control switches to marked positions indicative of preciselydefined percentages of the total timing cycle.

It is therefore the principle object of this invention to provide ahighly accurate and reliable traffic control cycle coordinator whichutilizes a digital implementation for deriving timing signalsrepresenting finite percentages of the total timing cycle available.

Other objects of this invention will become apparent from the followingdescription as taken in connection with the accompanying drawings, ofwhich:

FIG. I is a block diagram showing the general features of the invention,

FIG. 2 shows a series of waveforms illustrating the operation of oneembodiment ofthe system of the invention,

FIG. 3 is a functional schematic drawing illustrating one embodiment ofthe system of the invention, and

FIG. 4 is a functional schematic drawing illustrating an offset controlwhich may be utilized in the system of the invention.

Briefly described, the system of the invention operates as follows:Pulsating reference and control signals generated at a master stationare fed to each local traffic controller. These signals differ by afrequency such that the time interval between their in phase conditiondefines a timing cycle. A frequency multiplier at the local trafficcontroller is used for multiplying the frequency of the reference pulsesignal received from the master control station. The factor of thismultiplication defines the number of timing increments into which thetiming cycle is to be divided. The frequency multiplied signals are fedthrough a logical gating control to a counter which provides a trackinggate" signal synchronized with the multiplied pulses and at thefrequency of the reference signal. This tracking gate signal is comparedwith the control signal arriving from the master control station in acomparator circuit wherein a steering signal is generated whenever thetwo compared signals do not overlap each other. This steering signal isfed to the logical gating control to cause it to gate out a clock pulserepresenting one of the predetermined finite increments of the timingcycle.

While the logical control is gating this clock pulse, it fails toprovide a pulse to the counter, thereby delaying the arrival of thetracking gate by this one pulse and restoring the overlap between thetracking gate and the reference signal. This lock on condition duringwhich no clock pulses are gated out but frequency multiplied signals arecontinually fed to the counter, continues until the difference infrequency between the reference and control signals is again reflectedby a sufficient phase shift to cause a loss of overlap between thetracking gate signal and the reference signal, at which time anotherclock pulse is generated and the lock-on is again restored byeliminating one of the pulses fed to the counter. In this manner,successive clock pulses, each of which represents a precise finitepercentage of the total timing cycle, are generated with the trackinggate signal thus effectively tracking the reference signal.

Referring now to FIGS. 1 and 2 the basic operation of the system of theinvention is illustrated. Two pulsating signals T and T are fed frommaster control station 11 to the local station over telephone lines orthe like. These signals may be of the order of 400 cycles and differ bya frequency which determines the desired timing cycle. The period ofthis cycle as al ready noted is a direct function of the time betweenthe phase coincidence of the two signals. It is to be noted that T and Tmay originally be sine waves rather than in pulsating form, such sinewaves being squared and appropriately differentiated at the localstation to provide digital pulses suitable for processing by the digitalcircuitry involved. In an operative embodiment of the system of thisinvention, sine wave signals are so processed to derive digital pulsesfor T and T having a duration of an order of 10 microseconds. Thefrequency, f, of the cycle signal, T for any given desired timing cycle,Tcan be determined by the following equation:

: (frXT) 1 f. r W W (1) where f, is the frequency of the referencesignal T It thus can be seen that the timing cycle, T can be varied asdesired by changing f and this parameter is thus controlled in thismanner at the master control station.

The reference signal T is multiplied in frequency multiplier 13 toproduce signals T which are at a multiple of the frequency of T thismultiplication factor being equal to the number of finite incrementsinto which it is desired that the timing cycle be divided. It isessential that frequency multiplier 13 provide a precise multiplicationof pulses T so that pulses T are phase locked with T,, at all times andare at the precise desired multiple of the reference signal. Multiplier13 thus must be a highly accurate frequency multiplier, such as, forexample, one utilizing a voltage control oscillator which operates inconjunction with a phase lock circuit.

The frequency multiplied signal T is fed to 1 clock logical control 15which alternatively either feeds a single one of these pulses at a timeas a phase clock pulse T, to offset transition control 18 or as a trainof pulses T to counter 20. Counter 20 provides an output to comparatorcircuits 25 which is in synchronism with a predetermined one of thefrequency multiplied pulses T, and thus phase locked with referencesignal T This signal is compared for coincidence with the cycle controlsignal T,- in the comparator circuits 25 and a steering signal generatedwhich is fed to Q clock logical control in accordance with thiscomparison. As will be explained more fully further on in thespecification, when there is coincidence between the two, the frequencymultiplied signal T is fed through D clock logical control 15 to counter20. This represents a lock on" condition which is maintained at alltimes except when each of the phase clock signals T is being generated.A signal indicating such lock-on is fed from the comparator circuits 25to main timer 27 to indicate operation (and non-operation) of thiscircuit so that when a failure in operation occurs a standby clockgenerator (not shown) will be placed in operation.

Due to the difference in frequency between the cycle control pulses Tand the pulse signals received from counter which are phase locked withthe reference signal, T and define the tracking gate signal, T there isa gradual phase shift between these two signals which in the timingincrement determined by the multiplication factor of frequencymultiplier 13 results in a loss oflock-on. When this occurs, a steeringsignal is generated by comparator circuits which causes a single phaseclock pulse T to be passed from D clock logical control 15 to smoothoffset transition control 18 and to main timer 27 to provide a clockpulse therefor. While this single phase clock pulse is being gated out,there is no pulse T being gated from the logical control 15 to counter20 thus slowing up the pulse count within this counter such as torestore lock-on, i.e., time coincidence between the signal fed fromcounter 20 and cycle control pulse T In this manner, phase clock pulsesT, are generated to represent each incremental shift in phase betweensignals T R and T the number of such increments in each timing cyclebeing determined by the multiplication factor of frequency multiplier13. The reference pulses T and the cycle control pulses T are fed to ANDgate which provides a signal indicative of phase coincidence betweenthese two signals.

This signal, Ta, which indicates the start of each master" timing cycle,is fed to smooth offset transition control 18. Offset transition control18 also receives the clock pulses, Ta from D clock logical control 15and the offset reference signals from offset control 29 and provides anadjustment in discrete steps of the timing of the local controller intosynchronism with the offset master control signal. A smooth offsettransition control which may be utilized with this system is describedin co-pending application Ser. No. 610,510 filed Jan. 18, 1967, now U.S.Pat. No. 3,483,508 and assigned to Tamar Electronics Industries, Inc.,the assignee of the instant application.

Referring now to FIG. 3, a functional schematic of one embodiment of thesystem of the invention is shown. In this particular embodiment, as nowto be described, the frequency of reference pulses T is higher than thatof the cycle control pulses T and the frequency multiplication factor ofthe frequency multiplier is 100. It should be apparent, however, thatthe system of the invention can operate equally well with differentfrequency multiplication factors and with an opposite frequencyrelationship between T and T to that now to be described. Referring nowadditionally to FIG. 2 which shows the various waveforms generated inthe system of the invention, reference signals T which originate inmaster control station 11 and which, as already noted, are squared anddifferentiated to produce short duration pulses, are fed to frequencymultiplier 13 wherein they are multiplied by precisely 100 times, thesemultiplied signals Tp being phase locked with reference signals T Themultiplied signals Tp are fed to AND gates 40, 41 and 42 of D clocklogical control 15.

Let us assume first that flip-flop stage B of flip-flop 46 is in theTRUE state, which as to be explained later on is the situationimmediately following the generation of a phase clock, Ta and duringlock on. Under such conditions, pulses T; will be passed through ANDgate 42 to 100 counter 20, the input pulses to this counter being shownin FIG. 2 as pulses T Counter 20 is a recycling counter whichsuccessively repeats its counting cycle. A signal is fed on the 95th and99th counts of the counter to flip-flop stages A and 8" respectively offlip-flop 45, thus generating a gate which is provided as gating signalT Gating signal T, is inverted by means of inverter 31 and the invertedoutput T, fed to NAND gate 47. NAND gate 47 also receives a pulse signal51 which corresponds to the leading edge of cycle control signal T thislast mentioned signal being differentiated in differentiator 52. NANDgate 47 is adapted to be responsive only to positive going signals suchas pulse 51 and non-responsive to negative going signals such as gatingsignal T The amplitude of gating signal T, is such that it effectivelynegates pulse 51 when these two are in time coincidence, i.e., preventspulse 51 from being passed through the gate under such conditions.

Let us assume that pulse 51 which corresponds to the leading edge ofcycle control pulse T does not fall within the tracking gate. Under suchconditions, NAND gate 47 will gate pulse 51 through to actuate stage A"of flip-flop to its TRUE state. Stage A of this flip-flop is connectedto provide an enabling signal to AND gate 65, and the 0" output ofCounter 20 passes through this gate to actuate stage A" of flip-flop 68.Stage A" of flip-flop 68 provides an enabling signal to AND gates 40 and43. AND gate 40 will therefore pass a pulse T, to actuate stage A offlip-flop 46. Stage A" of flip-flop 46 in turn enables AND gate 41 whichpasses a I clock pulse, T.

At the same time AND gate 43 passes a T pulse to actuate stage A offlip-flop 49. This flip-flop in turn actuates stage A of flip-flop 70which operates as a reset latch to reset flipflops 68 and 60. With theresetting of flip-flop 68, the enabling signal is removed from AND gates40 and 43. Thus, no further I clock pulses Ta can be passed through ANDgate 41. At the same time stage B of flip-flop 68 provides an actuatingsignal to stage 8" of flip-flop 46 which enables AND gate 42 to againpass T pulses to counter 20.

Assuming that pulse 51 and tracking gate, T, do not arrive in timecoincidence, succeeding pulses 51 will cause the gating of successivesingle 1 clock pulses in the same manner just described. It is to benoted that each time a I clock pulse is gated, a T pulse is skipped, asshown, for example, in FIG. 2. This produces a time delay in thetracking gate, T, that causes it to rapidly fall into time coincidenceor lock-on" with pulse 51. it is to be noted that normally a search forlock-on only occurs when the equipment is first turned on and once thepulse 51 has initially fallen within the tracking gate to manifest alockon action, the pulse 51 (leading edge of T is never more than one Tpulse width out of the gate, as for example shown in the first cycleillustrated in FIG. 2.

As already noted, the cycle control pulses T are constantly shifting inphase with respect to the pulses T such that finally a pulse 51, whichrepresents the leading edge of T will drift out of the tracking gate TWhen the leading edge of this pulse T is no longer within the gate,i.e., has shifted so overlap is lost as shown in the first cycleillustrated in FIG. 2, NAND gate 47 will gate a TRUE output in responseto pulse 51 which will actuate flip-flop stage A of flip-flop 60. Thezero count of counter 20 is fed to AND gate 65, this gate also beingconnected to receive the output of flip-flop stage A of flip-flop 60.Therefore on the next 0 count of counter 20, a TRUE output will be fedfrom AND gate to actuate flipflop stage A" of flip-flop 68. The TRUEoutput signal from flip-flop stage A" of flip-flop 68 provides anenabling signal to AND gates 40 and 43. Therefore, the next T pulsewhich arrives at the input to AND gate 40 will actuate flip-flop stage Aof flip-flop 46 and also will be passed through AND gate 43 to actuateflip-flop stage A of flip-flop 49. With the actuation of flip-flop stageA" of flip-flop 46, AND gate 41 is enabled to pass a 1 clock pulse To inresponse to the next T pulse to arrive.

Only a single such I clock pulse is passed by virtue of the resetcircuits now to be described. As already noted, pulse T is also fedthrough AND gate 43 which is enabled by the same signal fed to AND gate40, this pulse operating to actuate flipflop stage A of flip-flop 49.The signal from flip-flop stage A" of flip-flop 49 operates to actuateflip-flop stage A of flip-flop 70, which operates as a reset latch.Flip-flop 70 provides a reset signal which drives the 33" stages offlip-flops 68 and 60. The B stage of flip-flop 68 actuates the 8" stageof flip-flop 46, thereby restoring the circuit to a condition whereby Tsignals are passed through AND gate 42 as T signals to counter 20 ratherthan through AND gate 41 as l clock signals. It is also to be noted thatwhen the reset signal is provided to flip-flop 68 it in turn provides agating signal to AND gate 62 which also receives a signal from flip-flop60 as it is reset. AND gate 62 thus has an output at this time whichdrives the B stages of flip-flops 40 and 70 to reset these flipflops fora succeeding cycle of operation.

Thus, the gating of phase clock pulses T and pulses T for counter 20 aremutually exclusive. As can be seen in FIG. 2, when a phase clock pulse,T is present, a pulse T to counter 20 is missing. Dropping of this one Tpulse results in a delay corresponding to one pulse in the arrival ofthe tracking gate T, relative to the cycle control pulse T causing thesepulses to fall back into coincidence as indicated in the second cycleshown in FIG. 2, thereby reestablishing lock-on. Thus, it will beapparent that each time pulse T shifts in phase one percent of the cyclewith respect to the reference pulse T with which the gate T, issynchronized, that the pulse T will have drifted" out of the gate,thereby initiating the generation ofa phase clock pulse andsimultaneously dropping one of the pulses, T fed to counter 20, therebycausing a restoration of a lock-on condition until another such onepercent timing increment has been completed. This operation thus repeatsitself over the entire timing cycle, generating 100 phase clock pulsesduring this period, each of such pulses representing a one percentincrement in this timing cycle.

It is to be noted that tracking gate T is purposely made fairly wide,i.e., to cover several pulse counts, this to facilitate lock-on andminimize the effects ofjitter on the signal which might erroneouslycause a loss of the lock-on condition. It is further to be noted that itmay also be desirable to place a digital filter in the comparatorcircuit such filter being implemented for example by means of abidirectional counter which will only provide the gating signal throughthe flip-flop 60 when a predetermined number of T pulses have beensuccessively received, thus minimizing the possibilities of anextraneous pulse on the line causing erroneous actuation of flip flop60.

Referring now to FIG. 4 an offset control 29 which may be utilized inthe system of the invention is illustrated. The cor rected 1 clockpulses arriving from Q clock logical control as corrected by the outputof smooth offset transition control 18 are fed to ten stage ring counter80, the output of which is connected to drive ten stage ring counter 82.These counters are the timing counters of main timer 27. Both countersare reset to zero by the C1 pulse in main timer 27, indicating theinitiation of main timer timing cycle. The counters may be those of atraffic control system such as described in connection with FIG. 3 ofUS. Pat. No. 3,376,546, issued Apr. 2, 1968. The C1,, pulse in thisinstance would be the reset signal arriving on line 68 or line 69. Theoffset control switches 83 and 84 would of course be connected to thecounter outputs in parallel with the other leads connected thereto toimplement the normal timing functions of the controller. Thus the ringcounters will successively count up to a hundred, counter 82 producingoutputs for zero and multiplies of 10 percent of this cycle whilecounter 80 produces outputs for zero and at l percent increments of thetiming cycle. Switches 83 and 84 may be set to select any desiredpercentage of the total timing cycle. Switches 83 and 84 are connectedthrough AND gate 86 to the smooth offset transition control 18. Thus,for example, with switches 83 and 84 set as indicated in FIG. 4, atiming signal will be fed to the smooth offset transition control 18each time percent of the timing cycle has been completed this signalbeing used to provide this selected offset timing. As can be seen inthis manner, any percentage of the total timing cycle can be selected toprovide an offset timing signal for main timer 27. The switches may,from a remote location.

The system of this invention thus provides highly accurate means forgenerating a timing signal precisely corresponding to a predeterminedpercentage of a timing cycle generated in a master control station. Thisimplementation is totally digital and utilizes a unique lock-ontechnique for generating successive signals representing the timingincrements.

We claim: 1. In a system for coordinating the timing operation of alocal traffic controller with timing signals generated at a mastercontrol station, said timing signals comprising first and seconddifferent frequency pulsating signals, a timing cycle being defined bythe interval between successive phase coincidence between said signals,the improvement comprising means in the local controller for digitallygenerating signals indicative of precise increments of the timing cycle,said improvement including:

frequency multiplier means for multiplying the frequency of said firstsignal by a multiplication factor corresponding to the number of thetiming increments to be generated,

logical control means for receiving the multiplied output of saidfrequency multiplier means,

means responsive to the multiplied signal output of said logical controlmeans for generating a tracking gate signal synchronized with apredetermined timing increment of said multiplied signal and at afrequency corresponding to said first signal,

comparator means for comparing said tracking gate signal for timecoincidence with said second signal,

said comparator means generating a steering signal for said logicalcontrol means to cause said logical control means to generate a phaseclock pulse corresponding to one of the increments of said timing cyclewhen the tracking and second signals are not in time coincidence and forfeeding said multiplied signal to said means for generating a trackinggate signal when the tracking and second signals are in timecoincidence.

2. The system of claim 1 wherein said means for generating a trackinggate signal comprises a counter for counting said multiplied signaloutput fed thereto from said logical control means and a flip-flopconnected to receive the outputs of two predetermined stages of saidcounter, one of said outputs operating to set the flipflop, the other ofsaid outputs operating to reset the flipflop, the tracking gate signalbeing the flipflop output.

3. The system of claim 1 and further including offset control means forgenerating a signal in accordance with a selected number of said timingcycle increments, pulses corresponding to said increments being fed tosaid offset control means.

4. The system of claim 3 wherein the main timer of said local trafficcontroller includes a counter and said offset control means includesselector switch means for selecting a predetermined count output of saidcounter.

5. The system of claim 1 wherein said logical control means includesreset circuit means for permitting only a single incremental 1 clockpulse output for each timing increment.

6. A system for generating timing signals representing preciseincrements of a timing cycle comprising:

means for generating first and second pulsating signals having apredetermined difference in frequency, the period between which saidsignals are in phase coincidence defining said timing cycle,

means for multiplying said first pulsating signal by a factordeterminative of the number of said timing cycle increments in eachcycle,

counter means,

offset transition control means,

logical control means for receiving the multiplied signal andalternatively feeding said multiplied signal to said counter means or tosaid offset transition control means,

said counter means being adapted to successively count to a number ofbits equal to said multiplying factor.

of course include relays set means responsive to said counter means forgenerating a tracking gate signal at the frequency of aid firstpulsating signal and synchronized with a predetermined bit count of saidcounter means, and

means for comparing said tracking gate signal and said second pulsatingsignal for time coincidence,

said logical control means being responsive to the output of saidcomparing means and operating to feed said multiplied signal as a phaseclock pulse (T b) to said offset transition control means when saidsecond pulsating signal and said gate signal are not in coincidence andto feed said multiplied signal (T to said counter means when said secondpulsating signal and said tracking gate signal are in coincidence,

whereby each time one of said phase clock pulses is fed to .said offsettransition control means, the timing of said tracking gate signal isdelayed so as to tend to restore coincidence between said tracking gatesignal and said second pulsating signal.

7. The system of claim 6 and further including offset control means forselectively setting a predetermined timing offset into said system.

8. In a system for coordinating the timing operation of a local trafficcontroller from a master station, said master station including meansfor generating pulsating reference and control signals having apredetermined small difference in frequency, the period between whichsaid signals are in phase coincidence defining a timing cycle, theimprovement being means for generating digital timing signals definingprecise increments of said timing cycle comprising:

frequency multiplier means for precisely multiplying said referencesignal by a factor corresponding to the number of said timing incrementsin each cycle,

counter means for dividing the output of said multiplier means by saidfactor,

means responsive to said counter means for generating a tracking gatesignal synchronized with a predetermined bit of said counter means,

means for comparing said gate signal and said control signal for timecoincidence, and

logical control means interposed between said multiplier means and saidcounter means and responsive to the output of said comparing means forcontrolling the tracking of said control signal by said tracking gatesignal, said control means alternatively feeding the output of saidmultiplier means to said counter means when said gate signal and saidcontrol signal are in time coincidence and providing a pulse output ofsaid multiplier means as an incremental phase clock pulse timing signalon the arrival of each control signal whenever said gate and controlsignals are not in time coincidence.

9. The system of claim 8 wherein said means for generating a trackinggate signal comprises a flipflop connected to receive the output of saidpredetermined counter means bit as a set signal and anotherpredetermined bit output of said counter means as a reset signal.

10. The system of claim 8 wherein said logical control means includesreset circuit means for permitting only a single incremental timingpulse output for each of the predetermined timing increments.

11. The system of claim 8 and further including AND gate means forgenerating a timing reference signal when the reference and controlsignals are in phase coincidence.

12. The system of claim 8 wherein said comparing means comprises a NANDgate for providing a signal to said logical control means in response tosaid control signal only when said control signal and said gate signalare not in time coincidence.

13. A method for coordinating the timing operation of a local trafficcontroller with a master control station comprising the steps of:

generating reference and cycle control pulsating signals at the masterstation, said signals differing in frequency by an amount defining atimin cycle, transmitting said signals to said local controller,

multiplying said reference signal by a factor defining increments ofsaid timing cycle,

generating a tracking gate signal synchronized with one of the timingincrements of said multiplied signals and at the frequency of saidreference signal,

comparing said tracking gate signal and said cycle control signal fortime coincidence, and

logically gating out one pulse of said multiplied signal at a time, inresponse to a cycle control signal, as a clock signal, whenever thetracking gate signal and the cycle control signal are not in timecoincidence.

1. In a system for coordinating the timing operation of a local trafficcontroller with timing signals generated at a master control station,said timing signals comprising first and second different frequencypulsating signals, a timing cycle being defined by the interval betweensuccessive phase coincidence between said signals, the improvementcomprising means in the local controller for digitally generatingsignals indicative of precise increments of the timing cycle, saidimprovement including: frequency multiplier means for multiplying thefrequency of said first signal by a multiplication factor correspondingto the number of the timing increments to be generated, logical controlmeans for receiving the multiplied output of said frequency multipliermeans, means responsive to the multiplied signal output of said logicalcontrol means for generating a tracking gate signal synchronized with apredetermined timing increment of said multiplied signal and at afrequency corresponding to said first signal, comparator means forcomparing said tracking gate signal for time coincidence with saidsecond signal, said comparator means generating a steering signal forsaid logical control means to cause said logical control means togenerate a phase clock pulse corresponding to one of the increments ofsaid timing cycle when the tracking and second signals are not in timecoincidence and for feeding said multiplied signal to said means forgenerating a tracking gate signal when the tracking and second signalsare in time coincidence.
 2. The system of claim 1 wherein said means forgenerating a tracking gate signal comprises a counter for counting saidmultiplied signal output fed thereto from said logical control means anda flip-flop connected to receive the outputs of two predetermined stagesof said counter, one of said outputs operating to set the flipflop, theother of said outputs operating to reset the flipflop, the tracking gatesignal being the flipflop output.
 3. The system of claim 1 and furtherincluding offset control means for generating a signal in accordancewith a selected number of said timing cycle increments, pulsescorresponding to said increments being fed to said offset control means.4. The system of claim 3 wherein the main timer of said local trafficcontroller includes a counter and said offset control means includesselector switch means for selecting a predetermined count output of saidcounter.
 5. The system of claim 1 wherein said logical control meansincludes reset circuit means for permitting only a single incrementalPhi clock pulse output for each timing increment.
 6. A system forgenerating timing signals representing precise increments of a timingcycle comprising: means for generating first and second pulsatingsignals having a predetermined difference in frequency, the periodbetween which said signals are in phase coincidence defining said timingcycle, means for multiplying said first pulsating signal by a factordeterminative of the number of said timing Cycle increments in eachcycle, counter means, offset transition control means, logical controlmeans for receiving the multiplied signal and alternatively feeding saidmultiplied signal to said counter means or to said offset transitioncontrol means, said counter means being adapted to successively count toa number of bits equal to said multiplying factor, means responsive tosaid counter means for generating a tracking gate signal at thefrequency of aid first pulsating signal and synchronized with apredetermined bit count of said counter means, and means for comparingsaid tracking gate signal and said second pulsating signal for timecoincidence, said logical control means being responsive to the outputof said comparing means and operating to feed said multiplied signal asa phase clock pulse (T Phi ) to said offset transition control meanswhen said second pulsating signal and said gate signal are not incoincidence and to feed said multiplied signal (Tp ) to said countermeans when said second pulsating signal and said tracking gate signalare in coincidence, whereby each time one of said phase clock pulses isfed to said offset transition control means, the timing of said trackinggate signal is delayed so as to tend to restore coincidence between saidtracking gate signal and said second pulsating signal.
 7. The system ofclaim 6 and further including offset control means for selectivelysetting a predetermined timing offset into said system.
 8. In a systemfor coordinating the timing operation of a local traffic controller froma master station, said master station including means for generatingpulsating reference and control signals having a predetermined smalldifference in frequency, the period between which said signals are inphase coincidence defining a timing cycle, the improvement being meansfor generating digital timing signals defining precise increments ofsaid timing cycle comprising: frequency multiplier means for preciselymultiplying said reference signal by a factor corresponding to thenumber of said timing increments in each cycle, counter means fordividing the output of said multiplier means by said factor, meansresponsive to said counter means for generating a tracking gate signalsynchronized with a predetermined bit of said counter means, means forcomparing said gate signal and said control signal for time coincidence,and logical control means interposed between said multiplier means andsaid counter means and responsive to the output of said comparing meansfor controlling the tracking of said control signal by said trackinggate signal, said control means alternatively feeding the output of saidmultiplier means to said counter means when said gate signal and saidcontrol signal are in time coincidence and providing a pulse output ofsaid multiplier means as an incremental phase clock pulse timing signalon the arrival of each control signal whenever said gate and controlsignals are not in time coincidence.
 9. The system of claim 8 whereinsaid means for generating a tracking gate signal comprises a flipflopconnected to receive the output of said predetermined counter means bitas a set signal and another predetermined bit output of said countermeans as a reset signal.
 10. The system of claim 8 wherein said logicalcontrol means includes reset circuit means for permitting only a singleincremental timing pulse output for each of the predetermined timingincrements.
 11. The system of claim 8 and further including AND gatemeans for generating a timing reference signal when the reference andcontrol signals are in phase coincidence.
 12. The system of claim 8wherein said comparing means comprises a NAND gate for providing asignal to said logical control means in response to said control signalonly when said control signal and said gate signal are not in timecoincidence.
 13. A method for coordinating the timing opEration of alocal traffic controller with a master control station comprising thesteps of: generating reference and cycle control pulsating signals atthe master station, said signals differing in frequency by an amountdefining a timing cycle, transmitting said signals to said localcontroller, multiplying said reference signal by a factor definingincrements of said timing cycle, generating a tracking gate signalsynchronized with one of the timing increments of said multipliedsignals and at the frequency of said reference signal, comparing saidtracking gate signal and said cycle control signal for time coincidence,and logically gating out one pulse of said multiplied signal at a time,in response to a cycle control signal, as a clock signal, whenever thetracking gate signal and the cycle control signal are not in timecoincidence.